1. Field
The following description relates to a plurality of semiconductor devices structure with multiple operating voltage and their manufacturing method with variable sidewall spacer length in one chip.
2. Description of Related Art
As the channel length decrease in the semiconductor device with sub-micron gate length, it is required to reduce the Hot Carrier Effect. Strong electric field adjacent to the drain region provides hot carrier electron to the gate insulator, which results in degradation of device performance due to breakdown of the gate insulator. Traditionally, the light doped drain region has been provided adjacent to highly doped drain region to solve this problem. The area of the Lightly Doped Drain (LDD) region is dependent on the size of sidewall spacer adjacent to gate electrode. As the sidewall spacer becomes longer, the length of lightly doped region also increases. If the device required higher operating voltage, the thickness gate insulator or the channel length should be modified. To make a plurality of semiconductor devices with multiple operation voltages in a one chip, the fabricating method is more complex than one single device in one chip.
There are many methods for fabricating a plurality of semiconductor devices with multiple operation voltages. For example, a method uses different silicon oxide growth rate. Nitrogen or a fluorine atom can be used to implant into the semiconductor substrate. However, such dopants requires further optimization process of ion implantation conditions. In addition, there are problems about device reliability degradation due to unwanted out-diffusion of fluorine atoms.